The hands on session on verilogHDL and FPGA which organized by the Reconfigurable Digital Systems Research Group was successfully held in the Analog and Digital electronic laboratories of the Department of Electronic and Telecommunication Engineering, University of Moratuwa. The goal of this session is to get undergraduate familiarize with the FPGA related technologies and to have hands on experience in getting started with digital design with verilogHDL.
Initially program was designed to accommodate 50-70 students in single laboratory, however due to the interest shown by the undergraduates; session was re-organized and conducted in two laboratories facilitating 120-130 students including semester two undergraduates to final year (level 4) undergraduates.
Workshop organized as two sessions; in the morning session it was more focused on digital design basics and basic digital system implementation on Xilinx FPGA using verilogHDL covering following topics.
- Logic minimization
- Half adder, full adder design
- Introduction to Verilog HDL
- Half adder implementation using verilogHDL generics
- 4-bit adder implementation using verilogHDL
- Introduction to Xilinx FPGA and Xilinx ISE
- Introduction to Atlys Spartan 6 Development Board
- Implementation of 4-bit adder on Atlys Spartan 6 Development Board
Evening session is more on Xilinx ISE including following topics.
- Introduction on Digital Design (Speech by Dr. Ajith Pasqual, Head of the Department)
- Test benches and simulations using Xilinx ISE and ISIM simulator
- Introduction on Xilinx Core generator for design acceleration
With the experience gained and feedback received from the undergraduates, it’s our expectation to improve and conduct more advanced workshops on digital design using Xilinx and Altera FPGAs in the future.