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3rd Hands on session on Digital Design with Verilog HDL and FPGA

Reconfigurable Digital System Group organizes their 3rd “Hands on session on Digital Design with Verilog HDL and FPGA" targeting batch ’10 and batch ’11 students of Dept. of Electronic and Telecommunication Engineering. The session will be held on 14th September 2013 from 8.30AM to 3.00PM at the Digital and Analog Laboratories depending on the number of students register for the event.

Workshop content will be as follows.

  1. Verilog Coding Styles. (Coding conventions, common mistakes and best practices.)
  2. State Machine Design Techniques. (Different styles of designing Mealy and Moore state machines.)
  3. Speed, Power and Area aware designing. (Meeting application goals.)
  4. Designing for FPGAs. (Take the maximum out of FPGA resources.)

Those who are interested in attending the workshops please verify your presence providing your details to THIS DOCUMENT.

Participants are requested to bring your own laptops with Altera and/or Xilinx installed and make sure to bring the FPGAs distributed among you all for the workshop as well. For further clarifications please email to This email address is being protected from spambots. You need JavaScript enabled to view it. .